• Boolean algebra and logic gates
• Combinational logic: adders, multiplexers, encoders
• Sequential logic: latches, flip-flops, registers
• Finite State Machines (FSMs)
• Implementation: from truth tables to circuits
• Timing, hazards, and synchronization
• Exercises

• Operators: AND, OR, NOT, XOR; identities: De Morgan, distributive, associative.
• Gate-level building blocks: NAND/NOR are functionally complete (can build any boolean function).
• Minimization: Karnaugh maps (K-maps), Quine–McCluskey.

// Truth table helper
function truthTable(vars, f){
  const rows = 1 << vars.length;
  const out = [];
  for (let i=0;i[v, (i>>idx)&1]));
    out.push({env, y: +!!f(env)});
  }
  return out;
}

• Multiplexer (MUX) selects among inputs; Decoder/Encoder convert between binary and one-hot.
• Half-adder and full-adder compose to ripple-carry adders; carry-lookahead reduces delay.
• ALU slices combine arithmetic and logic operations in datapaths.

• State via feedback. Latch (level-sensitive) vs Flip-Flop (edge-triggered); D, JK, T variants.
• Registers and shift-registers; register files as arrays of registers with read/write ports.
• Clocking strategies and metastability concerns at domain crossings.

• Moore vs Mealy machines: outputs depend on state only vs state+inputs.
• Design flow: specify states → draw diagram → create transition/output tables → encode → implement.
• State encoding: binary, one-hot, gray; trade-offs between flip-flops, speed, and logic.

// Simple FSM (conceptual) recognizing '101' over bits
const S0=0,S1=1,S2=2; let s=S0;
function step(bit){
  switch(s){
    case S0: s = bit?S1:S0; break;
    case S1: s = bit?S1:S2; break;
    case S2: s = bit?S1:S0; break;
  }
  return (s===S2 && bit===1); // emit when sequence seen
}

• Derive minimized boolean expressions, map to gates, or use multiplexers/PLAs for structured design.
• HDL synthesis (Verilog/VHDL) maps RTL to LUTs (FPGAs) or standard cells (ASICs).
• Hazard-aware implementations avoid glitches via proper factoring and timing.

// Verilog: Moore FSM skeleton
module fsm(input clk, input rst, input in, output reg out);
  typedef enum logic [1:0] {S0=2'b00,S1=2'b01,S2=2'b10} state_t;
  state_t s, s_next;
  always_ff @(posedge clk or posedge rst) begin
    if (rst) s <= S0; else s <= s_next;
  end
  always_comb begin
    s_next = s; out = 0;
    unique case (s)
      S0: s_next = in ? S1 : S0;
      S1: s_next = in ? S1 : S2;
      S2: begin out = in; s_next = in ? S1 : S0; end
    endcase
  end
endmodule

• Propagation and contamination delays; setup/hold constraints bound clock frequency.
• Combinational hazards (static/dynamic); fix with consensus terms or proper factoring.
• Clock domain crossing requires synchronizers (two-flop), FIFOs, or handshakes to avoid metastability.

1. Minimize a 4-variable boolean function using a K-map and implement with NAND gates only.
2. Design an FSM for a traffic light controller (Moore) and implement in Verilog.
3. Build a 4-bit ripple-carry adder and then a carry-lookahead adder; measure critical path.